1. Technical Field
This disclosure generally relates to testing and evaluation of electronic integrated circuits such as Application Specific Integrated Circuits (ASIC) and System-on-a-chip (SoC) designs, and more specifically relates to a method and apparatus for self evaluation of an integrated circuits such as an SoC or ASIC with multiple cores for Partial Good (PG) testing of the integrated circuit.
2. Background Art
Digital integrated circuits such as a system-on-a-chip (SoC) with ASIC or custom integrated circuit designs are becoming increasingly complex. SoC designs are including increasing numbers of microprocessor cores, some of which may be redundant for functional or manufacturing yield reasons. These multiple (microprocessor) cores are difficult to test and characterize as they are imbedded within the design. Multiple cores per die also increases manufacturing test time, complexity, and cost. As used herein, a “core” is a microcontroller, processor, digital signal processor (DSP) or other large block of circuitry that is replicated with a number of instances on an integrated circuit.
The testing of these devices is therefore becoming increasingly important. Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Ideally, it would be helpful to test the device for every possible defect. Because of the complexity of most devices, however, it is becoming prohibitively expensive to take the deterministic approach of testing every possible combination of inputs to each logic gate and states of the device. A more practical approach applies pseudorandom input test patterns to the inputs of the different logic gates. The outputs of the logic gates are then compared to the outputs generated by a “good” device (one that is known to operate properly) in response to the same pseudorandom input test patterns. The more input patterns that are tested, the higher the probability that the logic circuit being tested operates properly (assuming there are no differences between the results generated by the two devices.)
This non-deterministic approach can be implemented using built in test such as logic built-in self-test (LBIST) techniques. For example, one LBIST technique involves incorporating latches between portions of the logic being tested (the target logic,) loading these latches with pseudorandom bit patterns and then capturing the bit patterns that result from the propagation of the pseudorandom data through the target logic. Conventionally, the captured bit patterns are scanned out of the scan chains into a multiple-input signature register (MISR,) in which the bit patterns are combined with an existing signature value to produce a new signature value. This signature value can be examined (e.g., compared with the signature generated in a device that is known to operate properly) to determine whether or not the device under test functioned properly during the test.
In some devices, such as multiprocessor integrated circuits and SoC, the device may be considered to be “good,” even if some portions of the device include defects. For instance, in a SoC having multiple cores, the SoC may still be functional if one or more of the cores is defective. This is called Partial Good (PG) or PG testing.